Beyond the Transistor: How Memory, Light and Quantum Machines Are Redrawing the Computing Landscape

Foreign Affairs Forum | Dr. Antonio Bhardwaj (Dr. 🆎)| Nov 6th, 2026

Executive Summary

This FAF article examines five developments from the research window of Oct 30th to Nov 5th, 2026, that together show where the computing landscape is heading.

A Chinese-supported team reported ferroelectric transistors with a 20.6 V memory window, roughly 10⁶ switching cycles and stable six-bit operation. A separate team produced a superconducting superinductor on a commercial 22-nanometer GlobalFoundries process. IBM, AMD and Oak Ridge National Laboratory announced a quantum-supercomputing platform for error correction. Raytheon, part of RTX, won a Phase 1 DARPA contract for all-optical signal processing. And a peer-reviewed study sharpened how Ising machines should be judged. Reports of a Marvell pursuit of Lumentum add the commercial layer. The central finding is that progress now depends on integrating memory, logic, light and cooling rather than shrinking transistors alone, and that stakeholders must separate peer-reviewed measurement from corporate ambition.

Dr. 🆎 remarks that the most valuable skill this week is not enthusiasm but classification: knowing exactly what each announcement proves and what it does not.

Introduction

For half a century the computing story was told in one unit, the transistor. Every two years it shrank, and every shrink promised faster and cheaper machines. That story has not ended, but it no longer explains where the next gains will come from. Moving a bit of data now costs more energy than computing on it. Large artificial intelligence installations are limited by bandwidth, latency and power as much as by arithmetic.

As Dr. Antonio Bhardwaj, specialist in human-centered AI for geopolitical strategy, has argued in earlier FAF work, a nation's computing power is a property of its whole stack, from materials and foundries to interconnects, software and cooling.

This week's developments make that point vividly. None of them is a finished commercial product. Two are peer-reviewed laboratory measurements, one is a theoretical analysis, one is a research infrastructure announcement and one is a funded development contract. Read together, they describe a landscape in which memory is becoming part of computation, quantum devices are borrowing from the ordinary chip factory, light is taking over work from electrons, and classical supercomputers are becoming essential helpers for quantum machines.

This FAF article ranks the developments by scientific significance, strategic relevance and strength of evidence. It then traces the causes and effects connecting them and sets out the steps that matter for the coming years.

History and Current Status

The separation of processing and memory dates to the architecture adopted by the earliest electronic computers. The arrangement was elegant and flexible, but it created a permanent traffic problem. Data must shuttle between a memory and a processor, and as processors accelerated through the 20th century, the shuttle became the bottleneck. By the early 21st century, engineers were stacking memory closer to logic, widening buses and inventing caches, all to hide a cost that could not be removed.

Ferroelectric materials offered a different path from early on. A ferroelectric holds an electrical polarization that flips under an applied field and persists when power is removed. That makes it a natural candidate for nonvolatile memory, and for devices that store and process information in the same place. For years the difficulty was integration. Many ferroelectrics are incompatible with standard silicon processing, and their interfaces trap charge, which destabilizes the transistor threshold voltage. The arrival of nitride-based ferroelectrics such as aluminum scandium nitride changed the conversation, because these materials are closer to what chip fabrication already handles.

Superconducting electronics has an equally long history, with a recurring pattern. Laboratory demonstrations were impressive, but the components were made with bespoke techniques that did not scale. Quantum computing inherited this problem. Many quantum devices are built one at a time with customized steps, which is acceptable for physics experiments but not for production.

Quantum error correction is the third thread. Quantum bits are fragile. Reliable computation requires measuring them constantly, decoding the resulting signals and applying corrections, and that decoding is a heavy classical computation. Researchers have understood for years that a useful quantum computer would be a hybrid, but the practical organization of such a system has remained open.

Optical computing has the longest record of oscillation between promise and disappointment. Light offers enormous bandwidth, but optical systems demand lasers, tolerate little loss, react to temperature and must connect to electronic controllers. Meanwhile unconventional machines such as Ising machines, which encode optimization problems in interacting variables, have attracted claims of speed that were often hard to compare fairly with conventional processors.

Current status, as of Nov 6th, 2026, is therefore a field with many promising principles and few validated systems. This week supplied new evidence on each thread, and the evidence differs sharply in strength.

Key Developments

The first development, published on Nov 3rd in Nature Communications, concerns ferroelectric field-effect transistors built with aluminum scandium nitride and ultrathin indium gallium oxide channels.

The researchers attacked the two persistent problems, interface defects and threshold instability, by comparing device structures. The best results came from a metal–ferroelectric–metal–insulator–semiconductor configuration. It reached a memory window of 20.6 V, endurance near 10⁶ switching cycles and stable six-bit operation, meaning 64 distinguishable states in a single device. In a neuromorphic test the devices achieved 93.02% recognition accuracy under the study's conditions. The work also explored fabrication without a separate annealing step, which could ease thermal-processing demands.

The second development, published on Nov 4th in Nature Electronics, is a nonlinear superconducting circuit element called a superinductor, fabricated on the 22-nanometer fully depleted silicon-on-insulator process of GlobalFoundries.

The team exploited the kinetic inductance of titanium nitride films already present in that process and integrated the superinductor with a silicon quantum dot to build a radio-frequency single-electron transistor. The sensor occupied about 18 square micrometers and reported a power signal-to-noise ratio of 4,500 at a four-nanosecond integration time. The achievement is not merely a sensitive sensor. It is the demonstration that a specialized quantum-electronic component can come out of an established commercial CMOS line.

The third development, announced on Nov 5th, is the joint platform from IBM, AMD and Oak Ridge National Laboratory.

It combines IBM quantum processors, including the 120-qubit Nighthawk, with Oak Ridge's Umbra supercomputer, which uses AMD Instinct MI355X accelerators and fifth-generation EPYC processors. Its purpose is to study how classical machines can decode errors, optimize control and coordinate workflows for quantum processors, and to support research toward fault-tolerant architectures.

The fourth development, announced on Nov 3rd, is the Phase 1 contract awarded to Raytheon, the RTX business, by the Defense Advanced Research Projects Agency.

It sits within the PICASSO program, which stands for Photonic Integrated Circuit Architectures for Scalable System Objectives, and aims at an all-optical signal-processing system for demanding sensing and communications environments.

The fifth development, published on Nov 2nd in Communications Physics, is an analysis of classical adiabatic annealing on Ising machines.

It does not unveil a new device. Its value lies in rigor, clarifying how the performance of such specialized optimization hardware should be evaluated.

Beyond the five, reports during the week describe Marvell Technology pursuing a major acquisition of Lumentum, a deal that would join custom AI semiconductors, connectivity and optical components. It is a commercial signal rather than a scientific result.

Latest Facts and Concerns

The facts that can be stated with confidence are specific.

The ferroelectric transistor measurements, the superinductor characteristics and the Ising-machine analysis are published in peer-reviewed journals. The IBM, AMD and Oak Ridge platform is a confirmed research infrastructure initiative with a named hardware configuration. The Raytheon award is a confirmed Phase 1 research contract. The Marvell and Lumentum matter rests on reports and should be treated accordingly.

The concerns are equally specific, and they are the heart of this FAF article. A 93.02% recognition score on a neuromorphic task is not evidence that the transistor outperforms modern graphics processors or commercial memory. System-level performance will turn on switching energy, operating voltage, device variability, read and write circuitry and manufacturing yield, none of which the study establishes at commercial scale. Long-term retention under real operating conditions is likewise unproven.

The superinductor raises a different caution.

Superconducting operation generally requires refrigeration, so any efficiency comparison must count the electricity consumed by cooling. The sensor shows manufacturability of a component, not a complete quantum processor, high-volume production or reduced system power.

The IBM, AMD and Oak Ridge announcement does not demonstrate a new quantum advantage, a new cryptographic capability or fault-tolerant operation at commercial scale, and it does not show independently measured improvements in error correction. It builds the laboratory in which such measurements might later be made.

The photonics contract has its own limits. Phase 1 does not guarantee later procurement, no completed optical processor exists, and independently verified performance advantages and energy savings have yet to be shown. Optical systems must be judged after laser power, loss, thermal sensitivity and electronic integration are counted. The Ising-machine study explicitly does not establish a universal advantage over conventional processors, and energy efficiency must be measured for the entire system.

Dr. 🆎 offers a plain rule for readers: when an announcement states a device result, ask what the whole system would cost; when it states a contract or a deal, ask what has actually been demonstrated. None of the five developments proves a commercially validated gain in total data-center energy efficiency.

Cause-and-Effect Analysis

The first causal chain runs from the data-movement bottleneck to memory innovation.

Because moving information costs more than processing it, any device that stores and computes in one place attracts investment. That pressure explains the persistent interest in ferroelectric transistors. If multilevel, nonvolatile devices prove reliable, the effect would be less shuttling of data, lower standby power and a path to embedded AI processors. The cause is architectural, not fashionable. But the chain breaks if yield, variability or retention fail, which is why peer-reviewed endurance figures are only the first link.

The second chain runs from the scaling difficulty of quantum hardware to the value of mature foundry processes.

Bespoke fabrication cannot produce quantum machines in volume. A superinductor made on an established 22-nanometer line suggests that the cause, scaling difficulty, can be partly answered by borrowing industrial infrastructure. The effect is strategic. Countries and firms with strong mature-node manufacturing gain relevance in quantum and cryogenic electronics, and older process generations remain valuable even as the industry chases the newest nodes. The offsetting effect is thermal. Cooling consumes power, so integration gains can be erased at the system level.

The third chain runs from the fragility of quantum bits to heterogeneous computing.

Because errors must be detected and corrected continuously, classical computing becomes a permanent partner of quantum hardware. The effect is that accelerators, processors and quantum devices must be organized as one machine. For AMD, the effect is a new scientific showcase for its accelerators. For IBM, it supports scalable quantum architecture research. For the United States, it strengthens a research ecosystem across quantum and high-performance computing, with potential applications in materials science and energy research. The limit is that a platform is not a result.

The fourth chain runs from bandwidth limits to photonics.

Large AI installations suffer from bandwidth, latency and power constraints, so light is attractive both for processing and for interconnects. Defense demand for fast signal processing in radar, sensing and communications funds early research, and the effect may spill into optical switching, analog processing and integrated photonic components. The same cause explains the reported Marvell interest in Lumentum, since moving data between accelerators and servers is becoming as strategic as computing it. The counter-effect is engineering reality: lasers, losses, heat and electronic integration can consume the theoretical advantage.

The fifth chain concerns evidence itself. Alternative architectures attract attention because of claims of speed.

The cause of confusion is that comparisons depend on problem class, implementation, precision, algorithm choice and benchmark method. Rigorous analysis, such as the Ising-machine study, produces the effect of separating genuine architectural advantages from favorable benchmark selection, and it raises the bar for companies in unconventional computing, which must show advantages on meaningful workloads with transparent, reproducible benchmarks and realistic cost comparisons.

Finally, a geopolitical chain connects them.

China's support for the ferroelectric work illustrates continued investment in semiconductor technologies beyond conventional leading-edge silicon logic, a route that could eventually yield domestic memory architectures and specialized low-power computing. American activity is concentrated in quantum-classical platforms, photonics for defense and foundry-compatible quantum components. These are different bets, and the effect is a landscape in which competition is spread across the stack rather than concentrated at one chokepoint.

Future Steps

For advanced memory, the decisive future measurements are endurance, retention, write energy, operating voltage, manufacturing yield and integration cost.

Stakeholders should watch for independent replication and for results from complete memory arrays, not single devices.

For semiconductor manufacturing, commercial foundry compatibility could become a competitive advantage in specialized quantum and cryogenic electronics.

The next steps are integrating superinductor-based readout with larger arrays of quantum devices and reporting total system power, including cooling.

For large-scale computing, the most valuable architectures will be those that demonstrate measurable improvements on real scientific workloads.

The IBM, AMD and Oak Ridge platform should be judged by independently measured error-correction performance in the coming months and years, not by its announcement.

For optical interconnects and processing, the critical measurements remain bandwidth density, energy per transmitted bit, latency, reliability and total packaging cost.

A Phase 1 contract should be followed through its later phases, and any acquisition should be evaluated separately from experimental science.

For energy efficiency, the largest gains may come from coordinating processors, memory, interconnects, cooling and power delivery.

Device-level improvements should not be reported as data-center-level savings without appropriate measurements.

For venture capital and public markets, the research-driven areas worth monitoring are advanced memory materials, semiconductor manufacturing equipment, integrated photonics, quantum-control electronics and specialized computing software.

These developments support monitoring of emerging technologies rather than immediate investment decisions, and no peer-reviewed measurement or Phase 1 contract by itself signals an imminent product or listing. This is general information, not financial advice.

Conclusion

The defining lesson of the week is that computing leadership is becoming a competition across the entire technology stack. Ferroelectric transistors offer a possible alternative for storing information. Commercial CMOS lines are producing new superconducting components. Quantum research is being tied to classical supercomputing. Photonic processing continues to draw strategic investment. Specialized optimization machines are receiving harder scientific scrutiny.

The distinction that matters most is between a promising physical principle and a reliable commercial system. The technologies most likely to reshape the industry will combine scientific reproducibility, manufacturing scalability, measurable energy efficiency and competitive economics. Those criteria, not isolated laboratory records or corporate announcements, should decide how this FAF article's stakeholders judge the next generation of breakthroughs.

Dr. 🆎 closes with a simple point: the transistor is not being replaced, it is being surrounded, and the stakeholders who understand the whole stack will set the terms of the next decade.